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fm24c04b 4-kbit (512 8) serial (i 2 c) f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-84446 rev. *f revised april 21, 2014 256-kbit (32 k 8) serial (i 2 c) nvsram features 4-kbit ferroelectric random access memory (f-ram) logically organized as 512 8 ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see the data retention and endurance table) ? nodelay? writes ? advanced high-reliability ferroelectric process fast 2-wire serial interface (i 2 c) ? up to 1-mhz frequency ? direct hardware replacement for serial (i 2 c) eeprom ? supports legacy timings for 100 khz and 400 khz low power consumption ? 100 ? a active current at 100 khz ? 4 ? a (typ) standby current voltage operation: v dd = 4.5 v to 5.5 v industrial temperature: ?40 ? c to +85 ? c 8-pin small outline integrated circuit (soic) package restriction of hazardous substances (rohs) compliant functional overview the fm24c04b is a 4-kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes similar to a ram. it provides reliable data retention for 151 years while eliminating the complexities, overhead, and system-level reliability problems caused by eeprom and other nonvolatile memories. unlike eeprom, the fm24c04b performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately af ter each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product offers substantial write endurance co mpared with other nonvolatile memories. also, f-ram exhibits much lower power during writes than eeprom since write operations do not require an internally elevated power supply voltage for write circuits. the fm24c04b is capable of supporting 10 14 read/write cycles, or 100 million times more write cycles than eeprom. these capabilities make the fm24c04b ideal for nonvolatile memory applications, requirin g frequent or rapid writes. examples range from data loggin g, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the combination of features allows more frequent data writing with less overhead for the system. the fm24c04b provides substantia l benefits to users of serial (i 2 c) eeprom as a hardware drop-in replacement. the device specifications are guaranteed ov er an industrial temperature range of ?40 ? c to +85 ? c. address latch 512 x 8 f-ram array data latch 8 sda counter serial to parallel converter control logic scl wp a2-a1 9 8 logic block diagram
fm24c04b document number: 001-84446 rev. *f page 2 of 17 contents pinout ................................................................................ 3 pin definitions .................................................................. 3 overview............................................................................ 4 memory architecture........................................................ 4 i2c interface ...................................................................... 4 stop condition (p)..................................................... 4 start condition (s)................................................... 4 data/address transfer ................................................ 5 acknowledge / no-acknowledge ................................. 5 slave device address ............. .................................... 6 addressing overview (word ad dress) ........................ 6 data transfer .............................................................. 6 memory operation............................................................ 6 write operation ........................................................... 6 read operation ........................................................... 7 endurance ......................................................................... 8 maximum ratings............................................................. 9 operating range............................................................... 9 dc electrical characteristics .......................................... 9 data retention and endurance ..................................... 10 capacitance .................................................................... 10 thermal resistance........................................................ 10 ac test loads and waveforms..................................... 10 ac test conditions ........................................................ 10 ac switching characteristics ....................................... 11 power cycle timing ....................................................... 12 ordering information...................................................... 13 ordering code definitions ...... ................................... 13 package diagram............................................................ 14 acronyms ........................................................................ 15 document conventions ................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design supp ort............. .......... 17 products .................................................................... 17 psoc? solutions ...................................................... 17 cypress developer community................................. 17 technical support .................. ................................... 17
fm24c04b document number: 001-84446 rev. *f page 3 of 17 pinout figure 1. 8-pin soic pinout wp scl 1 2 3 4 5 nc 8 7 6 v dd sda a1 top view not to scale v ss a2 pin definitions pin name i/o type description a2-a1 input device select address 2-1 . these pins are used to select one of up to 4 devices of the same type on the same i 2 c bus. to select the device, the address va lue on the three pins must match the corre- sponding bits contained in the slave address. the address pins are pulled down internally. sda input/output serial data/address . this is a bi-directional pin for the i 2 c interface. it is open-drain and is intended to be wire-and'd with other devices on the i 2 c bus. the input buffer incorporates a schmitt trigger for noise immunity and the output driver includes slope control for falling edges. an external pull-up resistor is required. scl input serial clock . the serial clock pin for the i 2 c interface. data is clocked out of the device on the falling edge, and into the device on the rising edge. the scl input also incorporates a schmitt trigger input for noise immunity. wp input write protect . when tied to v dd , addresses in the entire memory map will be write-protected. when wp is connected to ground, all addresses are wr ite enabled. this pin is pulled down internally. v ss power supply ground for the device. must be connected to the ground of the system. v dd power supply power supply input to the device.
fm24c04b document number: 001-84446 rev. *f page 4 of 17 overview the fm24c04b is a serial f-ra m memory. the memory array is logically organized as 512 8 bits and is accessed using an industry-standard i 2 c interface. the functional operation of the f-ram is similar to serial (i 2 c) eeprom. the major difference between the fm24c04b and a serial (i 2 c) eeprom with the same pinout is the f-ram's superior write performance, high endurance, and low power consumption. memory architecture when accessing the fm24c04b, the user addresses 512 locations of eight data bits each. these eight data bits are shifted in or out serially. the addresses are accessed using the i 2 c protocol, which includes a slave address (to distinguish other non-memory devices), a page address bit, and a word address. the word address consists of 8- bits that specify one of the 256 addresses. the page address is 1-bit and so there are 2 pages of 256 locations. the complete address of 9-bits specifies each byte address uniquely. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the i 2 c bus. unlike a serial (i 2 c) eeprom, it is not necessary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted into the device, a write operation is complete. this is explained in more detail in the interface section. note that the fm24c04b contains no power management circuits other than a simple internal power-on reset. it is the user?s responsibility to ensure that v dd is within data sheet tolerances to prevent incorrect operation. i 2 c interface the fm24c04b employs a bi-directional i 2 c bus protocol using few pins or board space. figure 2 illustrates a typical system configuration using the fm24c04b in a microcontroller-based system. the industry standard i 2 c bus is familiar to many users but is described in this section. by convention, any dev ice that is sending data onto the bus is the transmitter while the target device for this data is the receiver. the device that is controlling th e bus is the master. the master is responsible for generating the clock signal for all operations. any device on the bus that is being controlled is a slave. the fm24c04b is always a slave device. the bus protocol is controlled by transition states in the sda and scl signals. there are four conditions including start, stop, data bit, or acknowledge. figure 3 and figure 4 illustrates the signal conditions that specify the four states. detailed timing diagrams are shown in the elec trical specifications section. stop condition (p) a stop condition is indicated when the bus master drives sda from low to high while the scl signal is high. all operations using the fm24c04b should end with a stop condition. if an operation is in progress when a st op is asserted, the operation will be aborted. the master must have control of sda in order to assert a stop condition. start condition (s) a start condition is indicated when the bus master drives sda from high to low while the sc l signal is high. all commands should be preceded by a start condition. an operation in progress can be aborted by asserting a start condition at any time. aborting an operation using the start condition will ready the fm24c04b for a new operation. if during operation the power supply drops below the specified v dd minimum, the system should issue a start condition prior to performing another operation. figure 2. system configuration using serial (i 2 c) nvsram microcontroller vcc sda scl vcc vcc 1 a 1 a 1 a a2 a2 a2 l c s l c s l c s sda a d s a d s p w p w p w #0 #1 #3 r pmin = (v dd - v ol max) / i ol r pmax = t r / (0.8473 * c b )
fm24c04b document number: 001-84446 rev. *f page 5 of 17 data/address transfer all data transfers (including addresses) take place while the scl signal is high. except under the three conditions described above, the sda signal should not change while scl is high. acknowledge / no-acknowledge the acknowledge takes place after the 8th data bit has been transferred in any transaction. during this state the transmitter should release the sda bus to allow the receiver to drive it. the receiver drives the sda signal low to acknowledge receipt of the byte. if the receiver does no t drive sda low, the condition is a no-acknowledge and the operation is aborted. the receiver would fail to acknowledge for two distinct reasons. first is that a byte transfer fa ils. in this case, the no-acknowledge ceases the current operation so that the device can be addressed again. this allows the last byte to be recovered in the event of a communication error. second and most common, the receiver does not acknowledge to deliberately end an operation. for example, during a read operation, the fm24c04b will co ntinue to place data onto the bus as long as the receiver sends acknowledge s (and clocks). when a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. if the receiver acknowledges the last byte, th is will cause the fm24c04b to attempt to drive the bus on the next clock while the master is sending a new command such as stop. figure 3. start and stop conditions full pagewidth sda scl p stop condition sda scl s start condition figure 4 data transfer on the i 2 c bus handbook, full pagewidth s or p sda s p scl stop or start condition s start condition 2 3 4 - 8 9 ack 9 ack 78 12 msb acknowledgement signal from slave byte complete acknowledgement signal from receiver 1 figure 5 acknowledge on the i 2 c bus handbook, full pagewidth s start condition 9 8 2 1 clock pulse for acknowledgement no acknowledge acknowledge data output by master data output by slave scl from master
fm24c04b document number: 001-84446 rev. *f page 6 of 17 slave device address the first byte that the fm24c04b expects after a start condition is the slave address. as shown in figure 6 , the slave address contains the device type or slave id, the device select address bits, a page select bit, and a bit that specifies if the transaction is a read or a write. bits 7-4 are the device type (slave id) and should be set to 1010b for the fm24c04b. these bits allow other function types to reside on the i 2 c bus within an identical address range. bits 3-2 are the device select address bits . they must match the corre- sponding value on the external address pins to select the device. up to four fm24c04b devices can reside on the same i 2 c bus by assigning a different address to each. bit 1 is the page select bit. it specifies the 256-byte blo ck of memory that is targeted for the current operation. bit 0 is the read/write bit (r/w ). r/w = ?1? indicates a read operation and r/w = ?0? indicates a write operation. addressing overview (word address) after the fm24c04b (as receiver) acknowledges the slave address, the master can place t he word address on the bus for a write operation. the word address is the lower 8-bits of the address to be combined with the 1-bit page select to specify exactly the byte to be written. the complete 9-bit address is latched internally. no word address occurs for a read operation. reads always use the lower 8-bits that are held internally in the address latch and the 9th address bit is part of the slave address. reads always begin at the address following the previous access. a random read address can be loaded by doing a write operation as explained below. after transmission of each data byte, just prior to the acknowledge, the fm24c04b increments the internal address latch. this allows the next sequential byte to be accessed with no additional addressing. after the last address (1ffh) is reached, the address latch will roll ov er to 000h. there is no limit to the number of bytes that ca n be accessed with a single read or write operation. data transfer after the address bytes have been transmitted, data transfer between the bus master and the fm24c04b can begin. for a read operation the fm24c04b will place 8 data bits on the bus then wait for an acknowledge from the master. if the acknowledge occurs, the fm24c04b will transfer the next sequential byte. if the acknowledge is not sent, the fm24c04b will end the read operation. for a write operation, the fm24c04b will accept 8 data bits from the master then send an acknowledge. all data transfer occurs msb (most significant bit) first. memory operation the fm24c04b is designed to operate in a manner very similar to other i 2 c interface memory products. the major differences result from the higher perfo rmance write capability of f-ram technology. these improvements result in some differences between the fm24c04b and a similar configuration eeprom during writes. the complete operation for both writes and reads is explained below. write operation all writes begin with a slave addre ss, then a word address. the bus master indicates a write operation by setting the lsb of the slave address (r/w bit) to a '0'. after addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condit ion. any number of sequential bytes may be written. if the end of the address range is reached internally, the address counter will wrap from 1ffh to 000h. unlike other nonvolatile memory technologies, there is no effective write delay with f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through th e bus. the entire memory cycle occurs in less time than a single bus clock. therefore, any operation including read or writ e can occur immediately following a write. acknowledge polling, a technique used with eeproms to determine if a write is complete is unnecessary and will always return a ready condition. internally, an actual memory write occurs after the 8th data bit is transferred. it will be complete before the acknowledge is sent. therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8th data bit. the fm24c04b uses no page buffering. the memory array can be writ e-protected using the wp pin. setting the wp pin to a high condition (v dd ) will write-protect all addresses. the fm24c04b will not acknowledge data bytes that are written to protected addresses. in addition, the address counter will not increment if wr ites are attempted to these addresses. setting wp to a low state (v ss ) will disable the write protect. wp is pulled down internally. figure 7 and figure 8 below illustrate a single-byte and multiple-byte write cycles. figure 6. memory slave device address handbook, halfpage r/w lsb msb slave id 10 1 0 a2 a0 a1 device select page select figure 7 single-byte write s a slave address 0 word address a data byte a p by master by f-ram start address & data stop acknowledge
fm24c04b document number: 001-84446 rev. *f page 7 of 17 read operation there are two basic types of read operations. they are current address read and selective address read. in a current address read, the fm24c04b uses the internal address latch to supply the lower 8 address bits. in a se lective read, the user performs a procedure to set these lower address bits to a specific value. current address & sequential read as mentioned above the fm24c04b uses an internal latch to supply the lower 8 address bits for a read operation. a current address read uses the existing value in the address latch as a starting place for the read opera tion. the system reads from the address immediately following th at of the last operation. to perform a current address read, the bus master supplies a slave address with the lsb set to a '1'. this indicates that a read operation is requested. the page select bit in the slave address specifies the block of memory that is used for the read operation. after receiving the complete slave address, the fm24c04b will begin shifting out data from the current address on the next clock. the current address is the bit from the slave address combined with the 8-bits that were in the internal address latch. beginning with the current addres s, the bus master can read any number of bytes. thus, a seq uential read is simply a current address read with multiple byte transfers. after each byte the internal address counter will be incremented. note each time the bus master acknowledges a byte, this indicates that the fm24c04b should read out the next sequential byte. there are four ways to properly terminate a read operation. failing to properly terminate the read will most likely create a bus contention as the fm24c04b attempts to read out additional data onto the bus. the four valid methods are: 1. the bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clo ck cycle. this is illustrated in the diagrams below. this is preferred. 2. the bus master issues a no-acknowledge in the 9th clock cycle and a start in the 10th. 3. the bus master issues a stop in the 9th clock cycle. 4. the bus master issues a start in the 9th clock cycle. if the internal address reaches 1ffh, it will wrap around to 000h on the next read cycle. figure 9 and figure 10 below show the proper operation for current address reads. figure 8. multi-byte write s a slave address 0 word address a data byte a p by master by f-ram start address & data stop acknowledge data byte a figure 9. current address read figure 10. sequential read s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data s a slave address 1 data byte 1 p by master by f-ram start address stop acknowledge no acknowledge data data byte a acknowledge
fm24c04b document number: 001-84446 rev. *f page 8 of 17 selective (random) read there is a simple technique that allows a user to select a random address location as the starting point for a read operation. this involves using the first two bytes of a write operation to set the internal address followed by subsequent read operations. to perform a selective read, the bus master sends out the slave address with the lsb (r/w ) set to 0. this specifies a write operation. according to the writ e protocol, the bus master then sends the word address byte that is loaded into the internal address latch. after the fm24c04b acknowledges the word address, the bus master issues a start condition. this simul- taneously aborts the write op eration and allows the read command to be issued with the slave address lsb set to a '1'. the operation is now a current address read. endurance the fm24c04b internally operates with a read and restore mechanism. therefore, endurance cycles are applied for each read or write cycle. the memory architecture is based on an array of rows and columns. each read or write access causes an endurance cycle for an entire row. in the fm24c04b, a row is 64 bits wide. every 8-byte boundar y marks the beginning of a new row. endurance can be optimized by ensuring frequently accessed data is located in different rows. regardless, f-ram read and write endurance is effectively unlimited at the 1-mhz i 2 c speed. even at 3000 accesses per second to the same row, 10 years time will elapse before 1 trillion endurance cycles occur. figure 11. selective (random) read s a slave address 1 data byte 1 p by master by f-ram start address stop no acknowledge data data byte a acknowledge s a slave address 0 word address a start address acknowledge
fm24c04b document number: 001-84446 rev. *f page 9 of 17 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +125 ? c maximum junction temperature ................................... 95 ? c supply voltage on v dd relative to v ss .........?1.0 v to +7.0 v input voltage .......... ?1.0 v to + 7.0 v and v in < v dd + 1.0 v dc voltage applied to outputs in high-z state .................................... ?0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ............ ..... ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount lead soldering temperature (10 seconds) ....................................... +260 ? c electrostatic discharge voltage human body model (aec-q100-002 rev. e) ..................... 3 kv charged device model (aec-q100-011 rev. b) ............. 1.25 kv machine model (aec-q100-003 rev. e) ............................ 250 v latch-up current .................................................... > 140 ma * exception: the "v in < v dd + 1.0 v" restriction does not apply to the scl and sda inputs. operating range range ambient temperature (t a ) v dd industrial ?40 ? c to +85 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [1] max unit v dd power supply 4.5 5.0 5.5 v i dd average v dd current scl toggling between v dd ? 0.3 v and v ss , other inputs v ss or v dd ? 0.3 v. f scl = 100 khz ? ? 100 ? a f scl = 400 khz ? ? 200 ? a f scl = 1 mhz ? ? 400 ? a i sb standby current scl = sda = v dd . all other inputs v ss or v dd . stop command issued. ?410 ? a i li input leakage current (except wp and a2-a1) v ss < v in < v dd ?1 ? +1 ? a input leakage current (for wp and a2-a1) v ss < v in < v dd ?1 ? +100 ? a i lo output leakage current v ss < v in < v dd ?1 ? +1 ? a v ih input high voltage 0.7 v dd ?v dd + 0.3 v v il input low voltage ? 0.3 ? 0.3 v dd v v ol output low voltage i ol = 3 ma ? ? 0.4 v r in [2] input resistance (wp, a2-a1) for v in = v il (max) 40 ? ? k ? for v in = v ih (min) 1??m ? v hys [3] input hysteresis 0.05 v dd ??v notes 1. typical values are at 25 c, v dd = v dd (typ). not 100% tested. 2. the input pull-down circuit is strong (40 k ? ) when the input voltage is below v il and weak (1 m ? ) when the input voltage is above v ih . 3. these parameters are guaranteed by design and are not tested.
fm24c04b document number: 001-84446 rev. *f page 10 of 17 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times .................................................10 ns input and output timing reference levels ................0.5 v dd output load capacitance ............................................ 100 pf data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ? c10?years t a = 75 ? c38? t a = 65 ? c 151 ? nv c endurance over operating temperature 10 14 ? cycles capacitance parameter [4] description test conditions max unit c o output pin capacitance (sda) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c i input pin capacitance 6pf thermal resistance parameter [4] description test conditions 8-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 147 ? c/w ? jc thermal resistance (junction to case) 47 ? c/w ac test loads and waveforms figure 12. ac test loads and waveforms 5.5 v output 100 pf 1.7 k ? 4. these parameters are guaranteed by design and are not tested.
fm24c04b document number: 001-84446 rev. *f page 11 of 17 ac switching characteristics over the operating range parameter [5] alt. parameter description min max min max min max unit f scl [6] scl clock frequency ? 0.1 ? 0.4 ? 1.0 mhz t su; sta start condition setup for repeated start 4.7 ? 0.6 ? 0.25 ? s t hd;sta start condition hold time 4.0 ? 0.6 ? 0.25 ? s t low clock low period 4.7 ? 1.3 ? 0.6 ? s t high clock high period 4.0 ? 0.6 ? 0.4 ? s t su;dat t su;data data in setup 250 ? 100 ? 100 ? ns t hd;dat t hd;data data in hold 0 ? 0 ? 0 ? ns t dh data output hold (from scl @ v il )0?0?0?ns t r [7] t r input rise time ? 1000 ? 300 ? 300 ns t f [7] t f input fall time ? 300 ? 300 ? 100 ns t su;sto stop condition se tup 4.0 ? 0.6 ? 0.25 ? s t aa t vd;data scl low to sda data out valid ? 3 ? 0.9 ? 0.55 s t buf bus free before new transmission 4.7 ? 1.3 ? 0.5 ? s t sp noise suppression time constant on scl, sda ? 50 ? 50 ? 50 ns figure 13. read bus timing diagram figure 14. write bus timing diagram t su:sda start t r ` t f stop start t buf t high 1/fscl t low t sp t sp acknowledge t hd:dat t su:dat t aa t dh scl sda t su:sto start stop start acknowledge t aa t hd:dat t hd:sta t su:dat scl sda notes 5. test conditions assume signal transition time of 10 ns or less, timing reference levels of v dd /2, input pulse levels of 0 to v dd (typ), and output loading of the specified i ol and load capacitance shown in figure 12 . 6. the speed-related specifications are guar anteed characteristic points along a continuous curve of operation from dc to f scl (max). 7. these parameters are guaranteed by design and are not tested.
fm24c04b document number: 001-84446 rev. *f page 12 of 17 power cycle timing over the operating range parameter description min max unit t pu power-up v dd (min) to first access (start condition) 1 ? ms t pd last access (stop condition) to power-down (v dd (min)) 0 ? s t vr [8, 9] v dd power-up ramp rate 30 ? s/v t vf [8, 9] v dd power-down ramp rate 30 ? s/v figure 15. power cycle timing sda ~ ~ ~ ~ t pu t vr t vf v dd v dd(min) t pd v dd(min) i c start 2 i c stop 2 notes 8. slope measured at any point on the v dd waveform. 9. guaranteed by design.
fm24c04b document number: 001-84446 rev. *f page 13 of 17 ordering information ordering code package diagram package type operating range FM24C04B-G 001-85066 8-pin soic industrial FM24C04B-Gtr all these parts are pb-free. contact your local cypre ss sales representative for availability of these parts. ordering code definitions option: blank = standard; t = tape and reel package type: g = 8-pin soic die revision = b density: 04 = 4-kbit voltage: c = 4.5 v to 5.5 v i 2 c f-ram cypress 24 fm c 04 b g tr -
fm24c04b document number: 001-84446 rev. *f page 14 of 17 package diagram figure 16. 8-pin soic (150 mils) package outline, 51-85066 51-85066 *f 51-85066 *f
fm24c04b document number: 001-84446 rev. *f page 15 of 17 acronyms document conventions units of measure acronym description ack acknowledge cmos complementary metal oxide semiconductor eia electronic industries alliance i 2 c inter-integrated circuit i/o input/output jedec joint electron devices engineering council lsb least significant bit msb most significant bit nack no acknowledge rohs restriction of hazardous substances r/w read/write scl serial clock line sda serial data access soic small outline integrated circuit wp write protect symbol unit of measure c degree celsius hz hertz kb 1024 bit khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt
fm24c04b document number: 001-84446 rev. *f page 16 of 17 document history page document title: fm24c04b, 4-kbit (512 8) serial (i 2 c) f-ram document number: 001-84446 rev. ecn no. submission date orig. of change description of change ** 3902082 02/25/2013 gvch new spec *a 3924523 03/07/2013 gvch changed t pu spec value from 10 ms to 1 ms *b 3996669 05/13/2013 gvch added appendix a - errata for fm24c04b *c 4045469 06/30/2013 gvch all errata items are fixed and the errata is removed. *d 4283418 02/19/2014 gvch converted to cypress standard format changed endurance value from 10 12 to 10 14 cycles updated maximum ratings table - removed moisture sensitivity level (msl) - added junction temperature and latch up current added input leakage current (i li ) for wp and a2-a1 updated data retention and endurance table added thermal resistance table removed package marking scheme (top mark) completing sunset review *e 4272607 03/12/2014 gvch typo fixed ( ac switching characteristics ): parameter spec unit changed from ns to s ? t su:sta , t hd:sta , t low , t high , t su:sto , t aa and t buf *f 4343617 04/21/2014 gvch typo fixed ( dc electrical characteristics ): v ol parameter spec unit changed from c to v
document number: 001-84446 rev. *f revised april 21, 2014 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. fm24c04b ? cypress semiconductor corporation, 2013-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wirelessfm24vn10 psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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